1. Field of the Invention
The present invention relates to a double data rate synchronous semiconductor memory device, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting into the outputted data a preamble notifying a start of data.
2. Description of the Related Art
Generally, a synchronous semiconductor memory device receives and outputs data in synchronization with an external system clock. Synchronous semiconductor memory devices are classified into single data rate synchronous semiconductor memory devices (hereinafter, referred to as SDR SDRAM) and double data rate synchronous semiconductor memory devices (hereinafter, referred to as DDR SDRAM).
While the SDR SDRAM operates in synchronization with rising edges or falling edges, the DDR SDRAM operates in synchronization with both rising edges and falling edges. Accordingly, the operation frequency of the DDR SDRAM is double that of the SDR SDRAM with respect to the same system clock. Since the DDR SDRAM transmits data at high frequency, a data strobe signal DS is used to latch such high frequency data.
A data strobe signal DS is generated by a data source when data is outputted. That is, when data is inputted from a master such a chipset or hub to a DDR SDRAM, the data strobe signal DS is generated by the master and inputted to the DDR SDRAM along with data. On the contrary, when data is outputted from the DDR SDRAM, the data strobe signal DS is generated in the DDR SDRAM and outputted to the master along with data. The side that receives the data recognizes input of data by the data strobe signal DS. That is, the data strobe signal DS plays a role of a synchronization clock for the semiconductor memory device to recognize data.
Such a data strobe signal DS keeps a high impedance state (between a high level and a low level) before the data are outputted from the data source. The data strobe signal DS is changed to a low level before one cycle from the time that data is outputted. The data strobe signal DS is toggled according to variation of a window of the data. After the data is outputted completely, the data strobe signal DS returns to a high impedance state.
FIG. 1 illustrates that a conventional semiconductor memory device using a data strobe signal receives and outputs data. Referring to FIG. 1, the conventional semiconductor memory device receives a command/address signal CA from a master in response to an externally input system clock CLK, and receives and outputs data DQ from and to the master using the data strobe signal DS generated by the data source.
FIG. 2 is a time chart of signals when data are inputted to the conventional semiconductor memory device shown in FIG. 1, that is, when the conventional semiconductor memory device shown in FIG. 1 receives a write command Write. FIG. 3 is a time chart of signals when the conventional semiconductor memory device shown in FIG. 1 receives a read command Read.
As shown in FIGS. 2 and 3, when the conventional semiconductor memory device receives a write command Write, the conventional semiconductor memory device receives data Q0-Q3 in synchronization with the center of the data strobe signal DS inputted from the master. When the conventional semiconductor memory device receives a read command Read, the conventional semiconductor memory device outputs the data strobe signal DS generated by the semiconductor memory device and the data Q0-Q3 in synchronization with an edge of the data strobe signal DS. However, since such a conventional semiconductor memory device does not have enough setup and hold time margins when receiving and outputting data, this limits data input/output operations of a memory that is required to have high speed.
FIG. 4 illustrates a memory module consisting of the conventional semiconductor memory device shown in FIG. 1, and particularly, an embodiment of a memory module suitable for a structure of a stub bus or a point-to-point bus.
Here, the structure of the stub bus or the point-to-point bus is a structure in which memories 502 and 506 included in memory modules 500 and 504 are connected to a connection line 508 on a board by point-to-point in connection structure for communication between memory modules, as shown in FIG. 5A. On the other hand, a short-loop-through (SLT) bus structure shown in FIG. 5B is a structure in which connection line 518 between memory modules 510 and 514 is connected via memories 512 and 516 of the memory modules 510 and 514. In general, the stub bus is not suitable for high frequency operation of 667 MHz or more. On the contrary, the SLT bus is a bus structure suitable for the high frequency operation of 667 MHz or more.
Referring to FIG. 4, the conventional memory module 400 includes a plurality of memories 100 and a register/PLL 402 for supplying the memories 100 with a system clock CLKm and an externally input command/address signal CAm and having a PLL circuit for synchronizing the signals. Data lines for inputting and outputting data DQ and signal lines for inputting and outputting the data strobe signal DS are connected to memories 100. However, since a path of the system clock CLKm supplied to the memories 100 and a path of the data strobe signal DS are set to be different from each other and the data strobe signal is individually connected to each memory 100, the path of the data strobe signal DS is comparatively short. On the other hand, the system clock CLKm has a comparatively long path through which the system clock CLKm is supplied from memories 406 and 408 near to the register/PLL 402 to memories 404 and 410 far from the register/PLL 402. Accordingly, if the operation frequency is increased, time skew can be caused by time delay of the system clock supplied to the memories of the memory module.